#include "kernel.h"

/* The LAPIC access */

// Local APIC registers, divided by 4 for use as uint[] indices.
#define ID      (0x0020/4)   // ID
#define VER     (0x0030/4)   // Version
#define TPR     (0x0080/4)   // Task Priority
#define EOI     (0x00B0/4)   // EOI
#define SVR     (0x00F0/4)   // Spurious Interrupt Vector
  #define ENABLE     0x00000100   // Unit Enable
#define ESR     (0x0280/4)   // Error Status
#define CMCI    (0x02F0/4)   // CMCI LVT
#define ICRLO   (0x0300/4)   // Interrupt Command
  #define INIT       0x00000500   // INIT/RESET
  #define STARTUP    0x00000600   // Startup IPI
  #define DELIVS     0x00001000   // Delivery status
  #define ASSERT     0x00004000   // Assert interrupt (vs deassert)
  #define LEVEL      0x00008000   // Level triggered
  #define BCAST      0x00080000   // Send to all APICs, including self.
#define ICRHI   (0x0310/4)   // Interrupt Command [63:32]
#define TIMER   (0x0320/4)   // Local Vector Table 0 (TIMER)
  #define X1         0x0000000B   // divide counts by 1
  #define PERIODIC   0x00020000   // Periodic
#define TMINT   (0x0330/4)   // Thermal Monitor
#define PCINT   (0x0340/4)   // Performance Counter LVT
#define LINT0   (0x0350/4)   // Local Vector Table 1 (LINT0)
#define LINT1   (0x0360/4)   // Local Vector Table 2 (LINT1)
#define ERROR   (0x0370/4)   // Local Vector Table 3 (ERROR)
  #define MASKED     0x00010000   // Interrupt masked
#define TICR    (0x0380/4)   // Timer Initial Count
#define TCCR    (0x0390/4)   // Timer Current Count
#define TDCR    (0x03E0/4)   // Timer Divide Configuration

static void
lapicw(int index, int value)
{
	 /* if (!sysconf.lapic_phys) */
	 /* 	  return; */
	 
	 lapic[index] = value;
	 lapic[ID];  // wait for write to finish, by reading
}

int
lapic_init(void)
{
	 /* if(!sysconf.lapic_phys)  */
	 /* 	  return 0; */

	 // Enable local APIC; set spurious interrupt vector.
	 lapicw(SVR, ENABLE | (IRQ_OFFSET + IRQ_SPURIOUS));

	 // The timer repeatedly counts down at bus frequency
	 // from lapic[TICR] and then issues an interrupt.  
	 // If xv6 cared more about precise timekeeping,
	 // TICR would be calibrated using an external time source.
	 lapicw(TDCR, X1);
	 lapicw(TIMER, PERIODIC | (IRQ_OFFSET + IRQ_TIMER));
	 lapicw(TICR, 10000000);

	 // Disable logical interrupt lines.
	 lapicw(LINT0, MASKED);
	 lapicw(LINT1, MASKED);

	 /* Disable the TM interrupt */
	 if(((lapic[VER]>>16) & 0xFF) >= 5)
		  lapicw(TMINT, MASKED);

	 // Disable performance counter overflow interrupts
	 // on machines that provide that interrupt entry.
	 if(((lapic[VER]>>16) & 0xFF) >= 4)
		  lapicw(PCINT, MASKED);

	 // Map error interrupt to IRQ_ERROR.
	 lapicw(ERROR, IRQ_OFFSET + IRQ_ERROR);

	 // Clear error status register (requires back-to-back writes).
	 lapicw(ESR, 0);
	 lapicw(ESR, 0);

	 // Ack any outstanding interrupts.
	 lapicw(EOI, 0);

	 // Send an Init Level De-Assert to synchronise arbitration ID's.
	 lapicw(ICRHI, 0);
	 lapicw(ICRLO, BCAST | INIT | LEVEL);
	 while(lapic[ICRLO] & DELIVS)
	 	  ;

	 // Enable interrupts on the APIC (but not on the processor).
	 lapicw(TPR, 0);

	 /* // Bochs doesn't support IMCR, so this doesn't run on Bochs. */
	 /* // But it would on real hardware. */
	 /* outb(0x22, 0x70);   // Select IMCR */
	 /* outb(0x23, inb(0x23) | 1);  // Mask external interrupts. */

	 return 0;
}

// Acknowledge interrupt.
void
lapic_send_eoi(void)
{
	 lapicw(EOI, 0);
}

// Spin for a given number of microseconds.
// On real hardware would want to tune this dynamically.
static void
microdelay(int us)
{
	 volatile int j = 0;
  
	 while(us-- > 0)
		  for (j=0; j<10000; j++);
}

#define IO_RTC  0x70

// Start additional processor running bootstrap code at addr.
// See Appendix B of MultiProcessor Specification.
int
lapic_startap(uint8_t apicid, uint32_t addr)
{
	 /* if (!sysconf.lapic_phys) */
	 /* { */
	 /* 	  return -E_UNSUPPORTED; */
	 /* } */
	 
	 int i;
	 uint16_t *wrv;
  
	 // "The BSP must initialize CMOS shutdown code to 0AH
	 // and the warm reset vector (DWORD based at 40:67) to point at
	 // the AP startup code prior to the [universal startup algorithm]."
	 outb(IO_RTC, 0xF);  // offset 0xF is shutdown code
	 outb(IO_RTC+1, 0x0A);
	 wrv = (uint16_t *)(0x40<<4 | 0x67);  // Warm reset vector
	 wrv[0] = 0;
	 wrv[1] = addr >> 4;

	 // "Universal startup algorithm."
	 // Send INIT (level-triggered) interrupt to reset other CPU.
	 lapicw(ICRHI, apicid<<24);
	 lapicw(ICRLO, INIT | LEVEL | ASSERT);
	 microdelay(200);
	 lapicw(ICRLO, INIT | LEVEL);
	 microdelay(100);	// should be 10ms, but too slow in Bochs!
  
	 // Send startup IPI (twice!) to enter bootstrap code.
	 // Regular hardware is supposed to only accept a STARTUP
	 // when it is in the halted state due to an INIT.  So the second
	 // should be ignored, but it is part of the official Intel algorithm.
	 // Bochs complains about the second one.  Too bad for Bochs.
	 for(i = 0; i < 2; i++){
		  lapicw(ICRHI, apicid<<24);
		  lapicw(ICRLO, STARTUP | (addr>>12));
		  microdelay(200);
	 }

	 return 0;
}

int
cur_cpu(void)
{
	 if (sysconf.use_lapic)
		  return lapic[ID];
	 else return 0;
}

int
send_ipi(int cpu, int func, int arg0, int arg1, int arg2, int arg3)
{
	 if (lapic[ICRLO] & DELIVS)
		  return -E_BUSY;
	 int cur = cur_cpu();
	 if (cur == cpu || cpus[cpu].valid == 0)
		  return -E_UNSUPPORTED;
	 spl_acquire(&cpus[cpu].ipi_recv_lock);
	 spl_acquire(&cpus[cpu].ipi_send_lock);
	 cpus[cpu].ipi_source = cur;
	 cpus[cpu].ipi_arg0 = arg0;
	 cpus[cpu].ipi_arg1 = arg1;
	 cpus[cpu].ipi_arg2 = arg2;
	 cpus[cpu].ipi_arg3 = arg3;
	 cpus[cpu].ipi_func = func;

	 lapic[ICRLO] = ASSERT | INT_IPI;
	 lapic[ICRHI] = cpu << 24;

	 while (cpus[cpu].ipi_send_lock != 0) ;
	 /* Is this be necessary? */
	 // while (lapic[ICRLO] & DELIVS) ;
}
